1. Field of the Invention
This invention relates to a semiconductor device having semiconductor chips stacked and mounted thereon and a manufacturing method thereof. More specifically, this invention relates to a package type semiconductor device of next generation called a COC (Chip On Chip) and a manufacturing method thereof and a semiconductor device called a stacked MCP (Multi-Chip Package) having the stacked and mounted semiconductor chips sealed in one package and a manufacturing method thereof.
2. Description of the Related Art
A stacked MCP in which the chip thickness and the package thickness are reduced is described in Jpn. Pat. Appln. KOAKAI Publication No. H10-70232, for example. This type of semiconductor device is formed by the following process. First, the backside of a semiconductor wafer which has been subjected to an element forming process is ground and etched and the wafer is reduced to desired thickness. Next, a DAF (Die attach film) or bonding agent such as epoxy resin is affixed to the backside of the semiconductor wafer and then the wafer is diced and cut apart into individual semiconductor chips. After this, the semiconductor chip is mounted on a printed circuit board or the like. Next, the semiconductor chip is electrically connected to printed wirings on the circuit board by wire bonding. Another semiconductor chip is stacked and mounted on the above semiconductor chip with a DAF disposed therebetween and the semiconductor chip is electrically connected to printed wirings on the circuit board by wire bonding. After this, the same process is repeatedly performed to sequentially stack semiconductor chips and a wire bonding process is performed for each chip. Then, the semiconductor chips stacked and mounted on the circuit board are sealed into a package of resin or the like.
When semiconductor chips with the same size are stacked on one another or a semiconductor chip larger than the semiconductor chip of the lower stage is stacked thereon, a spacer is affixed to the semiconductor chip of the lower stage with a DAF disposed therebetween in order to prevent the bonding wire from being brought into contact with the backside of the semiconductor chip of the upper stage. The spacer is smaller in size than the semiconductor chip of the lower stage, the outer peripheral portion thereof is set inside the bonding pads of the semiconductor chip of the lower stage and the spacer has thickness to provide a space which prevents the bonding wire of the chip of the lower stage from being brought into contact with the semiconductor chip of the upper stage when the semiconductor chip of the upper stage is mounted. Then, the semiconductor chip of the upper stage is mounted on the spacer with the DAF disposed therebetween and the bonding pads are electrically connected to the circuit board by wire bonding.
However, with the above structure and manufacturing method, the following problems (1) to (6) are provided.
(1) If the semiconductor wafer is diced with the DAF affixed thereon after the backside of the semiconductor wafer is ground, etched or the like to reduce the thickness thereof to desired thickness, chippings or cracks often occur on the backside of the chip.
(2) If the thickness of the semiconductor wafer is set to 70 μm or less, breakage of the wafer tends to occur and it becomes difficult to deal with the wafer. Further, since nothing is formed on the backside of the semiconductor chip while a protection film and wiring pattern are formed on the main surface thereof, a warp occurs due to a difference in the thermal expansion coefficient and the warp amount becomes several millimeters when the thickness is set to 30 μm. Therefore, it is not only difficult to deal with the chip, but also a recognition error occurs at the time of position detection by using an optical system such as a TV camera performed when the chip is stacked and mounted.
(3) Chip cracks often occur when individual semiconductor chips are picked up (separated) from a dicing tape after the semiconductor wafer is divided into the discrete chips. Further, when the thickness of the semiconductor chip becomes less than 100 μm, deflection (bending) occurs in the semiconductor chip when it is attracted by a collet and voids occur in the die-bonding (adhesion and pressure-connection) process.
(4) The semiconductor chip of the second stage or succeeding state is bent by pressurization at the ball bonding time because no rigid material is present under the bonding pad and the chip itself is thin and a lowering in the bonding property, for example, a loose connection and faulty connection position tend to occur. Further, if the bending amount of the chip is further increased, wire deformation and chip cracks occur in the semiconductor chip of the lower layer.
(5) When the semiconductor chips of the same size are stacked or the semiconductor chips of different sizes including a chip of the upper stage larger than the chip of the lower stage are stacked in the second and succeeding stages, it is necessary to dispose a spacer and DAF between the semiconductor chips and the package thickness cannot be made sufficiently small even if the semiconductor chip is made sufficiently thin. If the spacer and DAF are made thin, a short circuit or leak tends to occur between the bonding wire and the backside of the semiconductor chip stacked in the upper stage. Further, there occurs a possibility that the bonding wire flows to cause a short circuit at the time of resin-sealing.
(6) Costs for fabricating and bonding processes are necessary in addition to a material cost for the spacer and DAF, and as a result, the cost increases and the productivity is lowered.
The COC package type semiconductor device is described in Jpn. Pat. Appln. KOKAI Publication No. H05-063137 and Jpn. Pat. Appln. KOKAI Publication No. 06-120419. The semiconductor device of the above type is formed by the following process. First, semiconductor elements are formed on the main surface of a semiconductor wafer. Further, through electrodes electrically connected to the semiconductor elements are formed for the respective semiconductor chips. Next, the backside of the semiconductor wafer is ground and etched and the thickness of the wafer is reduced to desired thickness. After this, the backside of the semiconductor wafer is subjected to a CMP, plasma etching process and the like to cause the through electrodes to protrude. Next, a dicing process is performed to divide the wafer into discrete semiconductor chips. Then, the semiconductor chips formed by the above process are stacked and mounted in a multistage form on a printed circuit board having external connection electrodes. At this time, the through electrodes of the stacked semiconductor chips are electrically connected to one another via connection electrodes such as ball bumps or stud bumps inserted therebetween. After this, they are sealed into a package of resin or the like.
However, the above structure and manufacturing method have the following problems (7) to (10).
(7) If the semiconductor wafer is diced after the backside of the semiconductor wafer is ground and etched and the thickness of the wafer is reduced to desired thickness, chippings and cracks often occur on the backside of the chip.
(8) If the thickness of the semiconductor wafer is set to 70 μm or less, breakage tends to occur and it is difficult to deal with the wafer. Further, since nothing is formed on the backside of the semiconductor chip while a protection film and wiring pattern are formed on the main surface thereof, a warp occurs due to a difference in the thermal expansion coefficient and the warp amount becomes several millimeters when the thickness of the chip is set to 30 μm. Therefore, it is not only difficult to deal with the chip, but also a recognition error occurs at the time of position detection performed by using an optical system such as a TV camera when the chip is stacked and mounted.
(9) Chip cracks often occur when individual semiconductor chips are picked up (separated) from a dicing tape after the semiconductor wafer is divided into the discrete chips. Further, when the thickness of the semiconductor chip becomes less than 100 μm, deflection (bending) occurs in the semiconductor chip when it is attracted by a collet and voids occur in the die bonding process.
(10) When the semiconductor chips are stacked in a multistage form and mounted on a printed circuit board, the thicknesses of the connection electrodes of the respective chips are required in addition to the total sum of the thicknesses of the semiconductor chips to prevent a reduction in the thickness of the package.